Q. 47 A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK
flip-flop as follows. The Q output of the D flip-flop is connected to both the J and
K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected
to the input of the D flip-flop. Initially, the output of the D flip-flop is set to
logic one and the output of the JK flip-flop is cleared. Which one of the following
is the bit sequence (including the initial state) generated at the Q output of the
JK flip-flop when the flip-flops are connected to a free-running common clock
? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding
mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
(A) 0110110
(B) 0100100…
(C) 011101110…
(D) 011001100…
Answer: (A)
Explanation:
