Q. 55 A computer has a 256 KByte, 4-way set associative, write back data cache with block
size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each
cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified
bit and 1 replacement bit.
The size of the cache tag directory is
(A) 160 Kbits
(B) 136 Kbits
(C) 40 Kbits
(D) 32 Kbits
Answer: (A)
Explanation:
