Q. 41 Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with
combinational circuit only. The pipeline registers are required between each stage
and at the end of the last stage. Delays for the stages and for the pipeline registers
are as given in the figure.
What is the approximate speed up of the pipeline in steady state under ideal
conditions when compared to the corresponding non-pipeline implementation?
(A) 4.0
(B) 2.5
(C) 1.1
(D) 3.0
Answer: (B)
Explanation:
