Q. 21 Consider a hypothetical processor with an instruction of type LW R1, 20(R2),
which during execution reads a 32-bit word from memory and stores it in a 32-
bit register R1. The effective address of the memory location is obtained by the
addition of a constant 20 and the contents of register R2. Which of the following
best reflects the addressing mode implemented by this instruction for the operand
in memory?
(A) Immediate Addressing
(B) Register Addressing
(C) Register Indirect Scaled Addressing
(D) Base Indexed Addressing
Answer: (D)
Explanation:
